The present invention relates to a semiconductor device and a method of manufacturing it, and more specifically, to a structure of a semiconductor device having a stacked type capacitor and a manufacturing method thereof.
In the semiconductor device such as a dynamic random access memory (DRAM), as an integration level is increased, a chip area inevitably increases. To prevent the increase of a chip area, it is necessary to reduce the size of an individual memory cell. On the other hand, to obtain stable operation of the DRAM, it is necessary for a memory cell capacitor to maintain a capacitance of 20 fF to 30 fF. This value has not been changed even if the generation of DRAM takes turns. To satisfy contradicted requirements mentioned above, conventionally employed are capacitors have three dimensional structure such as a trench type or a stacked type.
A large scale DRAM having an integration level as high as a gigabit order is not sufficiently attained only by use of the three dimensional capacitor. Therefore, use of a dielectric film having a high, dielectric constant, such as a barium strontium titanate ((Ba, Sr) TiO3) film is required as the capacitor dielectric film,
FIG. 1 shows a sectional structure of a conventional stacked type DRAM memory cell employing the (Ba, Sr) TiO3 film as the dielectric film for a capacitor.
The DRAM memory cell comprises a silicon substrate 1, trench isolation 2, a gate electrode 3 of an MOS transistor for charging and discharging capacitor, a word line 4, a source region 5 and a drain region 6 of an MOS transistor, a contact region 6a for connecting a bit line and a silicon substrate, an insulating film 7 surrounding the gate and the word line, a polysilicon plug 10 for connecting the source region 5 of the MOS transistor to a storage node electrode 19, a polysilicon plug 11 for connecting the substrate to the bit line, and an insulating film 17 for isolating the MOS transistor from the capacitor.
A conventionally-employed process of manufacturing the stacked type capacitor (shown in FIG. 1) employing the (Ba, Sr) TiO3 as the dielectric film is as follows:
A contact hole is formed through the insulating film 17. Subsequently, a Ru film is deposited on the polysilicon plug 10 by a sputtering method and then subjected to patterning by conventionally-employed reactive ion etching (RIE) using SiO2 as an etching mask. As a result, the storage node electrode 19 is obtained.
On the patterned storage node electrode 19, a (Ba, Sr) TiO3 thin film 21 is deposited by metal organic chemical vapor deposition (MOCVD). Subsequently, a plate electrode 22 is formed of a Ru film on the (Ba, Sr) TiO2 thin film 21 by sputtering. In this manner, a stacked-type capacitor is accomplished.
In the conventionally-employed manufacturing process for the stacked-type capacitor mentioned above, the SiO2 film is first patterned on the Ru film by use of lithography in the form of an island. Then, the Ru film is etched by RIE using the SiO2 film as a mask, to form the storage node electrode 19.
The size of a gap (proximity gap) between adjacent island-form SiO2 mask pieces formed herein is defined by a resolution limit of lithography, so that the proximity gap between the Ru film pieces isolated by etching cannot fall within the size of the proximity gap of the SiO2 mask.
Conventionally, it is not always easy to etch the Ru film. To isolate the Ru film completely, the Ru film must be over-etched up to the peripheral region under the SiO2 mask. For this reason, the gap between adjacent storage node electrodes formed of the Ru film becomes inevitably larger than the proximity gap of the SiO2 mask defined by a lithographic resolution limit.
When the Ru film is etched by the RIE method, the side wall of the Ru film is formed nearly vertically. To improve step coverage of the (Ba, Sr) TiO3 thin film 21, the (Ba, Sr) TiO3 thin film must be formed by a CVD (chemical vapor deposition) method or an MOCVD method even if the deposition method has a problem in forming a film uniformly.
As described in the forgoing, there are many problems in the semiconductor device comprising the conventional stack-type capacitor and in the manufacturing method thereof. First, the number of manufacturing steps increases since the Ru film is etched by RIE using the SiO2 mask in two steps. Second, the storage capacity of the capacitor cannot be increased, since the proximity gap between the storage node electrodes made of the Ru film cannot be formed within the predetermined value defined by the lithographic resolution limit. Third, step coverage of the (Ba, Sr) TiO3 thin film is poor, since the side wall of the Ru film is formed nearly vertically.
The present invention was made to overcome the aforementioned problems. In the present invention, a depression is formed in the insulating film 17, a Ru film is formed in the inner wall of the depression instead of forming a storage node electrode 19 (Ru) formed on an insulating film 17 as in the conventional method. Therefore, a polysilicon plug 10 for connecting the storage node electrode 19 (Ru) to a source region 5 of a MOS transistor is formed on the bottom of the depression.
The inner wall of the depression crosses the upper surface of the insulating film at an interior angle within 90 to 110xc2x0. Since the aforementioned structure is made by flattening technology in combination with selective etching, the manufacturing steps can be reduced. As a result, the present invention is characterized by providing a semiconductor device and a method of manufacturing the semiconductor device having a highly reliable stacked type capacitor constructed with high degree of density.
To explain more specifically, in a first aspect, the semiconductor device of the present invention comprises:
a depression formed on a semiconductor substrate;
a conductive film formed in contact with a bottom face and an inner wall of the depression, the conductive film from an upper peripheral region of the depression being removed; and
an insulating film formed so as to cover an upper surface of the semiconductor substrate, the inner wall of the semiconductor substrate exposed in the upper peripheral region of the depression, and the conductive film.
In a second aspect, the semiconductor device of the present invention comprises:
a depression formed on the semiconductor substrate
a first electrode consisting of a conductive film formed in contact with a bottom face and an inner wall of the depression, the conductive film (constituting part of the first electrode) formed in the upper peripheral region of the inner wall of the depression being removed;
a dielectric film for a capacitor formed so as to cover an upper surface of the semiconductor substrate, the inner wall of the semiconductor substrate exposed in the upper peripheral region of the depression, and the first electrode; and
a second electrode formed of a conductive film formed in contact with the dielectric film for the capacitor.
In a third aspect, the semiconductor of the present invention comprises:
an insulating film formed on the semiconductor substrate;
a depression formed on the insulating film, a first electrode consisting of a conductive film formed in contact with a bottom face and an inner wall of the depression; the conductive film (constituting the first electrode) formed in the upper peripheral region of the depression being removed;
a dielectric film for a capacitor formed so as to cover an upper surface of the insulating film, the insulating film exposed in the upper peripheral region of the inner wall of the depression, and the first electrode; and
a second electrode consisting of a conductive film formed on and in contact with the dielectric film for the capacitor.
In a fourth aspect, the semiconductor device of the present invention comprises:
an insulating film formed on a semiconductor substrate;
a depression formed on the insulating film, a conductive plug reaching the semiconductor substrate is being exposed in part of the bottom face of the depression within the same plane as the bottom face;
a first electrode consisting of a conductive film formed in contact with a bottom face and an inner wall of the depression, the conductive film of first electrode formed in an upper peripheral region of the inner wall of the depression being removed;
at least one-layer dielectric film for a capacitor formed so as to cover an upper surface of the insulating film, the insulating film exposed in the upper peripheral region of the inner wall of the depression, and the first electrode; and
a second electrode consisting of a conductive film formed on and in contact with the dielectric film for the capacitor.
In a fifth aspect, the semiconductor device of the present invention comprises:
a MOS transistor having a source and drain formed on a semiconductor substrate;
an insulating film formed on the MOS transistor;
a depression formed on the insulating film, a conductive plug reaching either the source or the drain of the MOS transistor being exposed in part of the bottom face of the depression within the same plane as the bottom face;
a first electrode consisting of the conductive film formed in contact with a bottom face and an inner wall of the depression, the conductive film of the first electrode formed on the upper peripheral region of the depression being removed;
at least one-layer dielectric film for a capacitor formed so as to cover an upper surface of the insulating film, the insulating film exposed in the upper peripheral region of the inner wall of the depression, and the first electrode; and
a second electrode consisting of a conductive film formed on and in contact with the dielectric film for the capacitor.
In the semiconductor device of the present invention, it is preferable that either the semiconductor substrate with a depression or the upper surface of the insulating film formed on the semiconductor substrate cross the inner wall of the depression at an interior angle within the range of 90 to 110xc2x0.
In a sixth aspect, the semiconductor device of the present invention comprises:
a MOS transistor having a source and drain formed on a semiconductor substrate;
a first insulating film formed on the MOS transistor;
a first contact hole formed in the first insulating film and reaching either the source or the drain;
a conductive material filling in the first contact hole;
a second insulating film formed on the first insulating film and the conductive material;
a second contact hole formed in the second insulating film and reaching the conductive material;
a storage node electrode covering a bottom face and an inner wall of the second contact hole except an upper peripheral region of the inner wall of the second contact hole;
a dielectric film for a capacitor covering an upper surface of the second insulating film, the second insulating film exposed in the upper peripheral region of the inner wall of the second contact hole, and a surface of the storage node electrode; and
a plate electrode formed on and in contact with the dielectric film for the capacitor.
The dielectric film for a capacitor covering the upper surface of the second insulating film, the second insulating film exposed in the upper peripheral region of the inner wall of the second contact hole, and a surface of the storage node electrode has stepped portions in an interior and a peripheral region of the second contact hole. It is more preferable that all interior angles of the stepped portions fall within the range of 90 to 110xc2x0.
The method of manufacturing the semiconductor device of the present invention comprises the steps of:
forming a MOS transistor having a source and drain on a semiconductor substrate;
forming a first insulating film on the MOS transistor;
forming a first contact hole reaching either the source or the drain in the first insulating film;
filling a conductive material in the first contact hole;
forming a second insulating film on the first insulating film and the conductive material;
forming a second contact hole in the second insulating film so as to reach the conductive material;
forming a conductive film for a storage node electrode on an upper surface of the second insulating film and a bottom face and an inner wall of the second contact hole;
filling a third insulating film in a depression formed in a portion covering the bottom face and the inner wall of the second contact hole;
etching off the conductive film for the storage node electrode formed on the upper surface of the second insulating film using the third insulating film as a mask, simultaneously etching off the conductive film for the storage node electrode formed in an upper peripheral region of the inner wall of the second contact hole;
etching off the third insulating film;
forming a dielectric film for a capacitor over an entire capacitor formation region including the depression; and
forming a plate electrode on the dielectric film for the capacitor.
The step of filling the third insulating film in the depression preferably comprises forming the third insulating film on the conductive film for the storage node electrode and subsequently removing the third insulating film formed on the portion except the depression of the conductive film forming the storage node electrode by a chemical mechanical polish (CMP).
Furthermore, in the method of manufacturing the semiconductor device, it is preferable that SOG (spin on glass) be used as the third insulating film.
Still, in the method of manufacturing the semiconductor device, isotropic etching is employed in the step of etching off the conductive film for the storage node electrode formed on the second insulating film using the third insulating film as a mask, and in the simultaneously-performed step of etching off the conductive film for the storage node electrode formed in the upper peripheral region of the inner wall of the second contact hole.
The method of manufacturing the semiconductor device is characterized in that, in the step of forming the second contact hole in the second insulating film so as to reach the first conductive material, the surface of the second insulating film crosses the inner wall of the second contact hole at an interior angle within the range of 90 to 110xc2x0.
The method of manufacturing the semiconductor device is characterized in that, in the step of etching off the conductive film for the storage node electrode formed in the upper peripheral region of the inner wall of the second contact hole, the surface of the conductive film for the storage node electrode formed on the inner wall is etched in parallel to the upper surface of the second insulating film.
In another aspect, the method of manufacturing a semiconductor device comprising the steps of:
forming a MOS transistor having a source and drain on a semiconductor substrate;
forming a first insulating film on the MOS transistor;
forming a first contact hole reaching either the source or the drain in the first insulating film;
filling a conductive material in the first contact hole;
forming a second insulating film on the first insulating film and the conductive material;
forming a second contact hole in the second insulating film so as to reach the conductive material;
forming a conductive film for the storage node electrode on an upper surface of the second insulating film, and a bottom face and an inner wall of the second contact hole;
forming a third insulating film on the conductive film for the storage node electrode formed in the depression;
removing the third insulating film and the conductive film for the storage node electrode formed on the second insulating film except the depression by a CMP method;
etching off the conductive film for the storage node electrode formed in the upper peripheral region of the inner wall of the second contact hole using a third insulating film as a mask;
etching off the third insulating film;
forming a dielectric film for a capacitor over an entire capacitor formation region including the depression; and
forming a plate electrode on the dielectric film for the capacitor.
The storage node electrode mentioned above is formed of at least one element selected from the group consisting of Ru, Pt, Re, Os, Rh, Ir, oxides thereof, alloys and alloy oxides of the aforementioned elements, W, Nb, Al, Ti, Ta, Mo, Cu, WN, NbN, TiN, TaN, Pd. The dielectric film for the capacitor is formed of at least one element selected from the group consisting of (Ba, Sr) TiO3, BaTiO3, SrTiO3, PbZrO3, LiNbO3, Bi4Ti3O12, Ta2O5, and a multi-layered film formed of the aforementioned elements.
Additional object and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The object and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.